MINOTAUR: an edge transformer accelerator with on-chip RRAM
MINOTAUR is an energy-efficient edge SoC for inference and training of Transformers and CNNs with all memory on-chip, developed in the Stanford Robust Systems Group and presented at the IEEE Symposium on VLSI Technology and Circuits.
The chip combines a configurable posit-based accelerator with 12 MBytes of on-chip resistive RAM (RRAM) and fine-grained spatiotemporal power gating. As a visiting student researcher at Stanford, I co-developed the systolic array-based accelerator and engineered its power-aware ML compiler, featuring graph optimization and spatiotemporal power-gating that reduced overall power consumption by 40% while maintaining performance.
My master’s thesis, “Deployment of Deep Learning Workloads to Power-Constrained Platforms”, grew out of this work and covers the power-aware compiler in depth.
Paper: MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating (VLSI 2024)
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