Jekyll2026-07-12T17:17:48+00:00https://fabianpeddinghaus.com/feed.xmlblankPersonal website of Fabian Peddinghaus, ML compiler engineer at Axelera AI in Zurich. OmniMalloc: static memory allocation for neural networks2025-12-20T11:00:00+00:002025-12-20T11:00:00+00:00https://fabianpeddinghaus.com/blog/2025/omnimallocOmniMalloc is an open-source static memory allocation framework for neural networks. Ahead-of-time compilers for AI accelerators must place every tensor in scratchpad memory at compile time; doing this well is an NP-hard 2D packing problem that directly determines whether a network fits on-chip and how fast it runs.

OmniMalloc provides a collection of allocation algorithms behind a single interface, from fast heuristics to exact solver-based approaches, together with benchmarking and visualization tooling to compare them on real workloads.

I designed and open-sourced OmniMalloc while building the memory optimization passes of Axelera AI’s production compiler, where it is deployed today.

Code: github.com/fpedd/omnimalloc

]]>MINOTAUR: an edge transformer accelerator with on-chip RRAM2024-06-18T10:00:00+00:002024-06-18T10:00:00+00:00https://fabianpeddinghaus.com/blog/2024/minotaurMINOTAUR is an energy-efficient edge SoC for inference and training of Transformers and CNNs with all memory on-chip, developed in the Stanford Robust Systems Group and presented at the IEEE Symposium on VLSI Technology and Circuits.

The chip combines a configurable posit-based accelerator with 12 MBytes of on-chip resistive RAM (RRAM) and fine-grained spatiotemporal power gating. As a visiting student researcher at Stanford, I co-developed the systolic array-based accelerator and engineered its power-aware ML compiler, featuring graph optimization and spatiotemporal power-gating that reduced overall power consumption by 40% while maintaining performance.

My master’s thesis, “Deployment of Deep Learning Workloads to Power-Constrained Platforms”, grew out of this work and covers the power-aware compiler in depth.

Paper: MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating (VLSI 2024)

]]>muRISCV-NN: deep learning kernels for RISC-V microcontrollers2022-06-20T10:00:00+00:002022-06-20T10:00:00+00:00https://fabianpeddinghaus.com/blog/2022/muriscv-nnmuRISCV-NN is an open-source collection of efficient deep learning kernels for embedded RISC-V platforms and microcontrollers, which I created at TU Munich’s Department of Electronic Design Automation.

The library provides optimized kernels for the RISC-V Vector (RVV) and Packed (P) extensions, achieving up to 60% higher performance than LLVM’s auto-vectorizer. It exposes ARM CMSIS-NN compatible interfaces and integrates with TensorFlow Lite for Microcontrollers and microTVM, enabling seamless deployment of ML models on RISC-V hardware.

Code: github.com/tum-ei-eda/muriscv-nn

]]>A comparison of neural network computation architectures for low-power edge applications2022-02-21T11:00:00+00:002022-02-21T11:00:00+00:00https://fabianpeddinghaus.com/blog/2022/nn-architectures-low-power-edgeDuring my master’s at TU Munich I wrote a paper for the Advanced Seminar for VLSI Technology on how to run neural networks on low-power edge devices.

Offloading inference to the cloud adds latency, hurts reliability, and raises privacy concerns, so there is a strong case for running models directly on the device. The paper compares the three main hardware approaches for doing that: classical CPUs, vector processors, and specialized hardware accelerators, and looks at their efficiency and flexibility when running neural network workloads.

You can read the full paper here: PDF

]]>Spectrum sensing for the SALSAT nanosatellite2021-03-26T11:00:00+00:002021-03-26T11:00:00+00:00https://fabianpeddinghaus.com/blog/2021/spectrum-sensing-salsatFor my bachelor’s thesis at TU Berlin I developed and evaluated spectrum sensing algorithms for SALSAT, a nanosatellite that analyzes spectrum usage in low Earth orbit.

The work covers signal processing algorithms suitable for the tight compute and power budgets of a nanosatellite platform, evaluated on real and simulated spectrum data.

]]>UAV avionics with IFSys2020-09-15T10:00:00+00:002020-09-15T10:00:00+00:00https://fabianpeddinghaus.com/blog/2020/uav-avionics-ifsysAt TU Berlin’s Department of Flight Mechanics and Flight Control I worked as an undergraduate research assistant and was Technical Director of the student project IFSys, where we developed custom unmanned aerial systems.

I designed and published a distributed wireless control system that achieved 2× lower latency and higher reliability than a centralized baseline in real-world flight conditions.

]]>Heterogeneous computing: different concepts with different results2019-07-15T10:00:00+00:002019-07-15T10:00:00+00:00https://fabianpeddinghaus.com/blog/2019/heterogeneous-computingTogether with my fellow student Wladimir Assmann I wrote a paper for the Current Topics in Embedded Systems (CUTES) seminar at TU Berlin about heterogeneous computing.

Homogeneous multicore processors stop delivering the energy efficiency that embedded systems need, so architectures increasingly specialize individual cores or components for their workloads. The paper introduces heterogeneous computing, presents three different approaches to designing heterogeneous multicore processors, and compares them, with reported gains of over 60% in performance and up to 50% in energy delay product.

The paper is written in German. You can read it here: PDF

]]>Building a binary computer from transistors2016-03-04T11:00:00+00:002016-03-04T11:00:00+00:00https://fabianpeddinghaus.com/blog/2016/transistor-binary-computerIn high school I built a binary computer out of discrete transistors: adders, registers, and control logic soldered together from individual components.

The accompanying write-up (in German) documents the design and construction: PDF.

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